Energy-Efficient Multiplier Design Using Radix- 16 Booth Encoding and Clock Gating

In many computational areas, including DSP and machine learning, where speed and energy economy are critical, multiplication is an essential operation. The suggested Radix-16 Booth multiplier optimizes performance by using clock gating, 6-input LUTs, and 4:2 compressors. The experimental results demonstrate notable decreases in power consumption, critical path delay, and LUT utilization. This architecture is ideal for energy-constrained FPGA and VLSI systems because it balances speed, power, and resource efficiency.